RDNA Architecture

Key insights

6 takeaways

01
RDNA issues one instruction per cycle per SIMD32, whereas GCN issued one instruction every four cycles per SIMD16.See it on page 6
02
The document states that 256 threads per WGP often reach over 90% ALU utilization in practice, based on observations in pixel shaders from one game trace.See it on page 15
03
RDNA's Texture Units feature load addressing of 32 addresses per clock, compared with 4 to 16 coalesced addresses per clock on GCN.See it on page 34
04
RDNA adds a separate store queue, and non-atomic stores are described as fire-and-forget.See it on page 50
05
RDNA's L1 cache is 128KB per shader array with 128B cache lines, while Vega's L1 was 16KB per CU with 64B lines.See it on page 29
06
Under RDNA, each wave is assigned to one SIMD32 with up to 20 waves per SIMD32, while GCN assigned each wave to a SIMD16 with up to 10 waves per SIMD16.See it on page 7

Summary

This AMD presentation (its text references availability on July 7th) describes the RDNA GPU architecture and compares it with the earlier GCN architecture, using the RX 5700 XT (RDNA) and RX Vega 64 (GCN) as reference products. Its scope covers the Workgroup Processor (WGP) structure, instruction issue, wave sizes, register files, caches, load/store queues and memory hierarchy. The document presents RDNA as an architecture focused on graphics and latency, in contrast to GCN's compute and throughput focus. It states that each WGP provides resources of two Compute Units to a single workgroup and that Navi has 20 WGPs, corresponding to 40 CUs. On issue, it states that RDNA issues one instruction every cycle per SIMD32, where GCN issued one every four cycles per SIMD16. It also states that 256 threads per WGP often reach over 90% ALU utilization in practice, citing observations from pixel shaders in a game rendering trace. RDNA features 128B cache lines and a new 128KB L1 cache per shader array.

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