RDNA 3: Beyond the Current Gen

Key insights

7 takeaways

01
The RX 7900 XTX has 96 compute units and 960 GB/s of memory bandwidth, compared with 80 units and 512 GB/s on the RX 6900 XT.See it on page 5
02
On RDNA 3, the Infinity Cache is smaller than on RDNA 2 (96 MB versus 128 MB), but the document says the bandwidth gain is higher.See it on page 16
03
Splitting a workload into three blocks increased L0 cache hit rates by 37% on an AMD Radeon RX 6800XT, per the FSR 2 example.See it on page 17
04
The document advises using ExecuteIndirect with root signature changes avoided where possible, and recommends vertex pulling instead of updating vertex buffer bindings through ExecuteIndirect.See it on page 8
05
For shader write compression with a 4 BPE surface, the document says the best option is wave64 with an 8x8 thread-group, since wave32 cannot fully overwrite a 256-byte block.See it on page 14
06
The document recommends using one BLAS per mesh with one geometry index per material, rather than one BLAS per material, because splitting by material leads to significant instance overlap.See it on page 22
07
The document states that the RDNA 3 ray tracing architectural changes are evolutionary, and that traversal improvements target a common bottleneck in RT workloads.See it on page 18

Summary

This is an AMD presentation by Lou Kramer titled "RDNA 3: Beyond the Current Gen," offering performance guidance for developers on AMD's RDNA 3 GPU architecture. It covers draw and dispatch submission, ExecuteIndirect, compute shader wave sizes, memory bandwidth and compression, AMD Infinity Cache work tiling, and ray tracing BVH quality. The material compares the RX 5700 XT, RX 6900 XT and RX 7900 XTX. The comparison table lists 96 compute units and 960 GB/s memory bandwidth for the RX 7900 XTX, against 80 CUs and 512 GB/s for the RX 6900 XT. It also lists the RX 7900 XTX's Infinity Cache at 96 MB and its effective memory bandwidth at 3500 GB/s, against 128 MB and 1024 GB/s for the RX 6900 XT. In its work tiling example, the presentation reports that L0 cache hit rates increased 37% on an RX 6800 XT when a workload was split into three blocks. The document presents its guidance as recommendations for developers, and ends by advising that workloads be shaped to maximize cache effectiveness and compression be leveraged as much as possible.

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