NVIDIA Ada GPU Architecture

Key insights

6 takeaways

01
The AD102 GPU contains 76.3 billion transistors and 18,432 CUDA cores, operating at clock speeds exceeding 2.5 GHz.See it on page 4
02
The third-generation RT Core provides double the throughput for ray-triangle intersection testing compared to the Ampere architecture.See it on page 16
03
The Displaced Micro-Mesh Engine reduces BVH build time by a factor of 10x and storage requirements by 20x.See it on page 15
04
Shader Execution Reordering can improve overall performance by up to 44% in Cyberpunk 2077 running in RT: Overdrive Mode.See it on page 22
05
The L40 GPU delivers 90.5 TFLOPS of FP32 performance compared to 37.4 TFLOPS for the previous generation A40.See it on page 37
06
The Ada architecture's L2 cache has been increased to 98,304 KB in the AD102, a 16x improvement over the 6,144 KB found in the GA102.See it on page 12

Summary

The NVIDIA Ada GPU Architecture document details the technical specifications and architectural innovations of the Ada Lovelace GPU architecture, including the AD102 and AD103 chips. The architecture is designed for gaming, professional graphics, AI, and compute workloads, with specific implementations for consumer GeForce RTX 40-series cards and datacenter-focused L40 and L4 GPUs. The document outlines the transition from the previous Ampere architecture, highlighting improvements in manufacturing, power efficiency, and core processing capabilities.

Key architectural advancements include the third-generation RT Core, which introduces the Opacity Micromap Engine and the Displaced Micro-Mesh Engine to improve ray tracing efficiency and geometric complexity. The architecture also features Shader Execution Reordering to manage workload divergence and the fourth-generation Tensor Core, which supports the FP8 format. The document provides detailed comparative specifications for various GPU models, including CUDA core counts, cache sizes, and memory bandwidth, alongside performance metrics for ray tracing and AI-based tasks. The architecture utilizes the TSMC 4N manufacturing process to integrate up to 76.3 billion transistors in the AD102 flagship chip.